Most integrated circuits are created by exposing a pattern of features contained on a mask (sometimes referred to as a reticle) onto a silicon wafer that is coated with photosensitive materials. The exposed wafer is then chemically and mechanically processed to create corresponding objects or circuit elements on the wafer. Other circuit patterns are then exposed onto the wafer to build up the integrated circuit layer by layer.
As the circuit elements become smaller and smaller, the ability of a photolithographic printing system to print the features on the wafer becomes increasingly diminished. Optical and other process distortions occur such that the pattern contained on the mask will often not match the pattern of circuit elements that is printed on the wafer. To address this problem, numerous resolution enhancement techniques, such as optical and process correction (OPC) and other tools, such as phase shifting masks, subresolution assist features, etc., have been developed to enhance the fidelity with which a desired pattern can be printed on a wafer. One technique that is becoming increasingly used to print tightly packed features on a wafer is known as double patterning. In double patterning, a layout is parsed into two sets of polygons, with each set following design rules that allow it to be individually printable. Each set of polygons is then patterned onto the wafer. The phrase “double patterning” usually refers to a bright field, positive toned process, in which the polygons to be patterned are separated into two sets of dark (light blocking) polygons in an otherwise clear transparent field, and exposure to a mask with one set of polygons is completely processed (i.e. wafer coated with resist, and resist then exposed, developed and etched) before repeating the entire process again with a mask with the second set of polygons. Because the entire patterning sequence is repeated, this is called “double patterning”, as opposed to “double exposure”, where two exposures are made with different masks before the wafer is processed.
The present invention relates to improvements in multiple mask photolithographic printing techniques such as double patterning and double exposure processing techniques.